The present invention is directed to semiconductor devices, and more particularly to reducing current consumption of a semiconductor memory device.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, are manufactured using semiconductor fabrication technologies that are designed to reduce the size of the overall fabricated device. With the advancement of semiconductor fabrication technologies to smaller feature sizes, the ratio of so-called “leakage current” to overall operating current increases significantly. Leakage current is produced by circuits in the semiconductor device when certain voltage conditions associated with the circuit are present. There is also a trend in which semiconductor devices are to be designed to have minimal standby power consumption for use in mobile battery-powered host devices in order to support longer battery-powered operations. Thus, a tension exists between designing the smallest possible semiconductor device but still maximizing the power consumption efficiency of the semiconductor device. Such is the case with semiconductor memory and other integrated circuit devices.
One leakage current mechanism that has been mostly neglected until recently is called the gate induced drain leakage (GIDL). For example, one circuit component that is the building block of digital logic functions, including data storage (memory) circuits is the so-called field effect transistor. There are millions of these transistors in many semiconductor integrated circuit devices, and each has a drain terminal, gate terminal and source terminal. When there is a relatively high gate to drain voltage difference, electron/hole pairs are generated in the overlap region of the gate and drain/source diffusion region of the transistor. A current, called the GIDL current, is established between the drain/source region and the gate. The GIDL current mainly depends on the thickness of the oxide layer in the transistor, which in turn greatly depends on the feature size of the semiconductor fabrication technology used. For example, in semiconductor fabrication technologies less than or equal to 70 nm, the oxide layer is extremely thin making the gate to drain voltage difference quite significant. Nevertheless, only recently has the feature size of semiconductor process technologies become so small that reducing the GIDL current has become a design issue.
In designing semiconductor devices, such as DRAMs, it is important to suppress or eliminate the GIDL current in order to produce a product is competitive for power consumption sensitive applications.